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www.fairchildsemi.com rev. 1.0.2b 9/2/03 features highly ?xible dual synchronous switching pwm controller includes modes for: ddr mode with in-phase operation for reduced channel interference 90?phase shifted two-stage ddr mode for reduced input ripple dual independent regulators 180?phase shifted complete ddr memory power solution vtt tracks vddq/2 vddq/2 buffered reference output lossless current sensing on low-side mosfet or precision current sensing using sense resistor vcc under-voltage lockout ? ide power input range: 3 to 16v excellent dynamic response with voltage feed-forward and average current mode control ? o wer-good signal also supports ddr-ii and hstl tssop28 package applications ddr v ddq and v tt voltage generation desktop computer graphics cards general description the FAN5026 pwm controller provides high ef?iency and regulation for two output voltages adjustable in the range from 0.9v to 5.5v that are required to power i/o, chip-sets, and memory banks in high-performance computers, set top boxes, and vga cards. synchronous recti?ation contributes to high ef?iency over a wide range of loads. ef?iency is ev en further enhanced by using mosfets r ds(on) as a current sense component. feed-forward ramp modulation, average current mode control scheme, and internal feedback compensation provide f ast response to load transients. out-of-phase operation with 180 degree phase shift reduces input current ripple. the controller can be transformed into a complete ddr memory power supply solution by activating a designated pin. in ddr mode of operation one of the channels tracks the output voltage of another channel and provides output current sink and source capability ?features essential for proper powering of ddr chips. the buffered reference v oltage required by this type of memory is also provided. the FAN5026 monitors these outputs and generates separate pgx (power good) signals when the soft-start is completed and the output is within ?0% of its set point. a built-in ove r- v oltage protection prevents the output voltage from going above 120% of the set point. normal operation is automatically restored when the over-voltage conditions go aw ay. under-voltage protection latches the chip off when either output drops below 75% of its set value after the soft-start sequence for this output is completed. an adjust- able over-current function monitors the output current by sensing the voltage drop across the lower mosfet. if precision current-sensing is required, an external current- sense resistor may optionally be used. f an5026 dual ddr/dual-output pwm controller
product specification FAN5026 2 rev. 1.0.2b 9/2/03 generic block diagrams figure 1. dual output regulator figure 2. complete ddr memory power supply fan502 6 vin (battery) = 3 to 16v q1 c ou t1 vout1 = 2.5v dd r l out1 q2 c ou t2 vout2 = 1.8v l out2 pwm 1 pwm 2 ilim 1 ilim2/ ref 2 vcc +5 q3 q4 vin (battery ) fan502 6 q1 c out 1 vddq = 2.5v dd r l out1 q2 c out 2 vtt = vd dq/2 l out2 pwm 1 pwm 2 ilim 1 pg2/ref r r vcc +5 +5 ilim2/ref2 q3 q4 1.25v vin (battery) = 3 to 16v
FAN5026 product specification rev. 1.0.2b 9/2/03 3 pin con?urations pin de?itions pin number pin name pin function description 1a gnd analog ground . this is the signal ground reference for the ic. all voltage levels are measured with respect to this pin. 2 27 ldrv1 ldrv2 low-side drive . the low-side (lower) mosfet driver output. connect to gate of low-side mosfet. 3 26 pgnd1 pgnd2 power ground . the return for the low-side mosfet driver. connect to source of low-side mosfet. 4 25 sw1 sw2 switching node . return for the high-side mosfet driver and a current sense input. connect to source of high-side mosfet and low-side mosfet drain. 5 24 hdrv1 high-side drive . high-side (upper) mosfet driver output. connect to gate of high-side mosfet. 6 23 boot1 boot2 boot . positive supply for the upper mosfet driver. connect as shown in figure 3. 7 22 isns1 isns2 current sense input . monitors the voltage drop across the lower mosfet or external sense resistor for current feedback. 8 21 en1 en2 enable . enables operation when pulled to logic high. toggling en will also reset the regulator after a latched fault condition. these are cmos inputs whose state is indeterminate if left open. 9 20 gnd ground . these pins should be tied to agnd for proper operation. 10 19 vsen1 vsen2 output voltage sense . the feedback from the outputs. used for regulation as well as pg, under-voltage and over-voltage protection and monitoring. 11 ilim1 current limit 1 . a resistor from this pin to gnd sets the current limit. 12 17 ss1 ss2 soft start . a capacitor from this pin to gnd programs the slew rate of the converter during initialization. during initialization, this pin is charged with a 5 a current source. 13 ddr ddr mode control . high = ddr mode. low = 2 separate regulators operating 180?out of phase. agnd ldrv1 pgnd1 sw1 hdrv1 boot1 isns1 en1 gnd vsen1 ilim1 ss1 ddr vin FAN5026 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vcc ldrv2 pgnd2 sw2 hdrv2 boot2 isns2 en2 gnd vsen2 ilim2/ref2 ss2 pg2/ref2out pg1 tssop-28 ja = 90?/w
product specification FAN5026 4 rev. 1.0.2b 9/2/03 absolute maximum ratings absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. functional operation under these conditions is not implied. recommended operating conditions 14 vin input voltage . normally connected to battery, providing voltage feed-forward to set the amplitude of the internal oscillator ramp. when using the ic for 2-step conversion from 5v input, connect through 100k to ground, which will set the appropriate ramp gain and synchronize the channels 90?out of phase. 15 pg1 power good flag . an open-drain output that will pull low when vsen is outside of a ?0% range of the 0.9v reference. 16 pg2 / ref2out power good 2 . when not in ddr mode: open-drain output that pulls low when the vout is out of regulation or in a fault condition reference out 2 . when in ddr mode, provides a buffered output of ref2. typically used as the vddq/2 reference. 18 ilim2 / ref2 current limit 2 . when not in ddr mode, a resistor from this pin to gnd sets the current limit. reference for reg #2 when in ddr mode. typically set to vout1/2. 28 vcc vcc . this pin powers the chip as well as the ldrv buffers. the ic starts to operate when voltage on this pin exceeds 4.6v (uvlo rising) and shuts down when it drops below 4.3v (uvlo falling). p arameter min. typ. max. units vcc supply voltage 6.5 v vin 18 v boot, sw, isns, hdrv 24 v boot to sw 6.5 v all other pins ?.3 vcc+0.3 v junction temperature (t j ) ?0 150 ? storage temperature ?5 150 ? lead soldering temperature, 10 seconds 300 ? p arameter conditions min. t yp. max. units supply voltage vcc 4.75 5 5.25 v supply voltage vin 16 v ambient temperature (t a ) note 1 ?0 85 ? pin de?itions (continued) pin number pin name pin function description
FAN5026 product specification rev. 1.0.2b 9/2/03 5 electrical speci?ations recommended operating conditions, unless otherwise noted. p arameter conditions min. typ. max. units po wer supplies vcc current ldrv, hdrv open, vsen forced above regulation point 2.2 3.0 ma shut-down (en=0) 30 a vin current ?sinking vin = 15v 10 30 a vin current ?sourcing vin = 0v ?5 ?0 a vin current ?shut-down 1 a uvlo threshold rising vcc 4.3 4.55 4.75 v falling 4.1 4.25 4.45 v uvlo hysteresis 300 mv oscillator frequency 255 300 345 khz ramp amplitude, pk?k vin = 16v 2 v ramp amplitude, pk?k vin = 5v 1.25 v ramp offset 0.5 v ramp / vin gain vin 3v 125 mv/v ramp / vin gain 1v < vin < 3v 250 mv/v reference and soft start internal reference voltage 0.891 0.9 0.909 v soft start current (i ss ) at start-up ? a soft start complete threshold 1.5 v pwm converters load regulation i outx from 0 to 5a, vin from 5 to 15v -2 +2 % vsen bias current 50 80 120 na under-voltage shutdown as % of set point. 2 s noise filter 70 75 80 % over-voltage threshold as % of set point. 2 s noise filter 115 120 125 % i sns over-current threshold r ilim = 68.5k ? see figure 10. 112 140 168 a minimum duty cycle 10 % output drivers hdrv output resistance sourcing 12 15 ? sinking 2.4 4 ? ldrv output resistance sourcing 12 15 ? sinking 1.2 2 ?
product specification FAN5026 6 rev. 1.0.2b 9/2/03 figure 3. ic block diagram pg (power good output) and control pins lower threshold as % of set point, 2 s noise filter ?6 ?4 % upper threshold as % of set point, 2 s noise filter 108 116 % pg output low ipg = 4ma 0.5 v leakage current v pullup = 5v 1 a pg2/ref2out voltage ddr = 1, 0 ma < i ref2out < 10ma 99 1.01 % v ref2 ddr, en inputs input high 2v input low 0.8 v electrical speci?ations (continued) recommended operating conditions, unless otherwise noted. p arameter conditions min. typ. max. units il im ref 2 pgoo d en c boot q1 q2 5v vdd a daptive gate cont rol logic current processing hdrv sw ldrv pgnd boot vdd isns vin c ou t vou t pwm s/h r ilim r sense ilim det. ss pwm sr q ram ? p ddr osc i out ramp clk ovp por/ uvlo reference and soft start l out vref ea vsen vin ddr ddr
FAN5026 product specification rev. 1.0.2b 9/2/03 7 t ypical applications figure 4. ddr regulator application ta b le 1. ddr regulator bom notes: 1. suitable for applications of 4a continuous, 6a peak for vddq. if continuous operation above 6a is required use single so-8 packages for q1a (fds6612a) and q1b (fds6690s) respectively. using fds6690s, change r7 to 1200 ? . refer to power mosfet selection, page 14 for more information. 2. c6 = 2 x 180 f in parallel. description qty ref. vendor part number capacitor 68?, tantalum, 25v, esr 150m ? 1c 1 avx tpsv686*025#0150 capacitor 10nf, ceramic 2 c2, c3 any capacitor 68?, tantalum, 6v, esr 1.8 ? 1c 4 avx tajb686*006 capacitor 150nf, ceramic 2 c5, c7 any capacitor 180?, specialty polymer 4v, esr 15m ? 2 c6a, c6b panasonic eefue0g181r capacitor 1000?, specialty polymer 4v, esr 10m ? 1c 8 kemet t510e108(1)004as4115 capacitor 0.1?, ceramic 1 c9 any 1.82k ? , 1% resistor 3 r1, r2, r6 any 56.2k ? , 1% resistor 1 r3 any 10k ? , 5% resistor 1 r4 any 3.24k ? , 1% resistor 1 r5 any 1.5k ? , 1% resistor 2 r7, r8 any schottky diode 30v 2 d1, d2 fairchild bat54 inductor 6.4?, 6a, 8.64m ? 1l 1 panasonic etq-p6f6r4hfa inductor 0.8?, 6a, 2.24m ? 1l 2 panasonic etq-p6f0r8lfa dual mosfet with schottky 2 q1, q2 fairchild fds6986s (note 1) ddr controller 1 u1 fairchild FAN5026 2 c6 vddq = 2.5v ddr l1 q1b 5 27 vtt = vddq/2 l2 24 pwm 2 ilim1 pg2/ref 14 13 11 16 r5 r6 18 28 vcc +5 +5 ilim2/ref2 q2b 1.25v@10ma c7 d1 +5 6 4 r7 7 25 r8 23 d2 +5 22 c4 19 vsen2 isns2 1 agnd r3 3 26 pgnd2 sw2 h drv2 isns1 pgnd2 en1 8 en2 21 q1a q2a vsen1 r2 r1 ldrv1 b oot2 h drv1 sw1 b oot1 vin ldrv2 c5 c1 pg1 15 +5 r4 c9 ss1 12 c2 ss2 17 c3 c8 20 9 vin = 3 to 16v pwm 1 10
product specification FAN5026 8 rev. 1.0.2b 9/2/03 t ypical applications (continued) figure 5. dual regulator application ta b le 2. dual regulator bom note: 1. if currents above 4a continuous required, use single so-8 packages for q1a/q2a (fds6612a) and q1b/q2b (fds6690s) respectively. using fds6690s, change r6/r7 as required. refer to power mosfet selection, page 14 for more information. description qty ref. vendor part number capacitor 68?, tantalum, 25v, esr 95m ? 1c 1 avx tpsv686*025#095 capacitor 10nf, ceramic 2 c2, c3 any capacitor 68?, tantalum, 6v, esr 1.8 ? 1c 4 avx tajb686*006 capacitor 150nf, ceramic 2 c5, c7 any capacitor 330?, poscap, 4v, esr 40m ? 2 c6, c8 sanyo 4tpb330ml capacitor 0.1?, ceramic 2 c9 any 56.2k ? , 1% resistor 1 r1, r2 any 10k ? , 5% resistor 1 r3 any 3.24k ? , 1% resistor 1 r4 any 1.82k ? , 1% resistor 3 r5, r8, r9 any 1.5k ? , 1% resistor 2 r6, r7 any schottky diode 30v 2 d1, d2 fairchild bat54 inductor 6.4?, 6a, 8.64m ? 2 l1, l2 panasonic etq-p6f6r4hfa dual mosfet with schottky 1 q1 fairchild fds6986s (note 1) ddr controller 1 u1 fairchild FAN5026 2 c6 ddr l1 q1b 5 27 c8 1.8v@2a l2 24 pwm 1 pwm 2 ilim1 14 13 11 r4 r5 18 28 vcc +5 ilim2 q2b c7 d1 +5 6 4 r6 7 25 r7 23 d2 +5 9 22 c4 19 vsen2 isns2 1 r2 pg1 15 +5 3 26 pgnd2 sw2 h drv2 isns1 pgnd2 q1a q2a 20 r8 r9 10 vsen1 ldrv1 b oot2 h drv1 sw1 b oot1 vin ldrv2 c5 c1 vin r1 2.5v@4a pg2 16 en2 21 r3 c9 ss2 17 c3 agnd en1 8 ss1 12 c2 vin = 3 to 16v gnd gnd
FAN5026 product specification rev. 1.0.2b 9/2/03 9 circuit description overview the FAN5026 is a multi-mode, dual channel pwm control- ler intended for graphic chipset, sdram, ddr dram or other low output voltage power applications in pcs, vga cards and set top boxes. the ic integrates a control circuitry for two synchronous buck converters. the output voltage of each controller can be set in the range of 0.9v to 5.5v by an e xternal resistor divider. the two synchronous buck converters can operate from either an unregulated dc source (such as a notebook battery) with voltage ranging from 5.0v to 16v, or from a regulated system rail of 3.3v to 5v. in either mode of operation the ic is biased from a +5v source. the pwm modulators use an av erage current mode control with input voltage feed- forward for simpli?d feedback loop compensation and improved line regulation. both pwm controllers have integrated feedback loop compensation that dramatically reduces the number of external components. the FAN5026 can be con?ured to operate as a complete ddr solution. when the ddr pin is set high, the second channel can provide the capability to track the output voltage of the ?st channel. the pwm2 converter is prevented from going into hysteretic mode if the ddr pin is set high. in ddr mode, a buffered reference voltage (buffered voltage of the ref2 pin), required by ddr memory chips, is provided by the pg2 pin. converter modes and synchronization ta b le 3. converter modes and synchronization when used as a dual converter (as in figure 5), out-of-phase operation with 180 degree phase shift reduces input current ripple. f or the ?-step?conversion (where the vtt is converted from vddq as in figure 4) used in ddr mode, the duty c ycle of the second converter is nominally 50% and the optimal phasing depends on vin. the objective is to keep noise generated from the switching transition in one converter from in?encing the ?ecision?to switch in the other converter. when vin is from the battery, its typically higher than 7.5v. as shown in figure 6, 180?operation is undesirable since the turn-on of the vddq converter occurs very near the decision point of the vtt converter. figure 6. noise-susceptible 180?phasing for ddr1 in-phase operation is optimal to reduce inter-converter interference when vin is higher than 5v, (when vin is from a battery), as can be seen in figure 7. since the duty cycle of pwm1 (generating vddq) is short, its switching point occurs far away from the decision point for the vtt regulator, whose duty cycle is nominally 50%. figure 7. optimal in-phase operation for ddr1 when vin 5v, 180?phase shifted operation can be rejected for the same reasons demonstrated figure 6. in-phase operation with vin 5v is even worse, since the switch point of either converter occurs near the switch point of the other converter as seen in figure 8. in this case, as vin is a little higher than 5v it will tend to cause early termination of the vtt pulse width. conversely, vtts switch point can cause early termination of the vddq pulse width when vin is slightly lower than 5v. figure 8. noise-susceptible in-phase operation for ddr2 these problems are nicely solved by delaying the 2 nd converter's clock by 90?as shown in figure 9. in this way, all switching transitions in one converter take place far away from the decision points of the other converter. figure 9. optimal 90?phasing for ddr2 mode vin vin pin ddr pin pwm 2 w.r.t. pwm1 ddr1 battery vin high in phase ddr2 +5v r to gnd high + 90 dual any vin low + 180 vddq vtt cl k vddq vtt cl k vddq vtt cl k vddq vtt cl k
product specification FAN5026 10 rev. 1.0.2b 9/2/03 initialization and soft start assuming en is high, FAN5026 is initialized when vcc e xceeds the rising uvlo threshold. should vcc drop below the uvlo threshold, an internal power-on reset function disables the chip. the voltage at the positive input of the error ampli?r is lim- ited by the voltage at the ss pin which is charged with a 5 a current source. once c ss has charged to vref (0.9v) the output voltage will be in regulation. the time it takes ss to reach 0.9v is: where t 0.9 is in seconds if c ss is in f. when ss reaches 1.5v, the power good outputs are enabled and hysteretic mode is allowed. the converter is forced into pwm mode during soft start. current processing section the following discussion refers to figure 10. the current through r sense resistor (isns) is sampled shortly after q2 is turned on. that current is held, and summed with the output of the error ampli?r. this effec- tively creates a current mode control loop. the resistor connected to isnsx pin (r sense ) sets the gain in the current feedback loop. for stable operation, the voltage induced by the current feedback at the pwm comparator input should be set to 30% of the ramp amplitude at maximum load current and line voltage. the following expression estimates the recommended value of r sense as a function of the maximum load current (i load(max) ) and the value of the mosfets r ds(on) : r sense must, however, be kept higher than: figure 10. current limit / summing circuits t 0.9 0.9 c ss 5 ----------------------- = (1) r sense i load max () r ds on () 4.1k ? ? 30% 0.125 v in max () ? ? ----------------------------------------------------------------------------- 1 0 0 = (2a) r sense min () i load max () r ds on () ? 150 a ----------------------------------------------------------- 1 0 0 = (2b) l drv pgn d isns in + in 2. 5v ilim det. r sen se ss 1.5m c ss v sen v to i reference and soft start 17p f i1b = isns 9 i2 = 4 * ilim 3 ilim 0.9v r il im ilim mirro r s/h to pwm co mp 4.14k 300k i1a = isns 0. 17pf
FAN5026 product specification rev. 1.0.2b 9/2/03 11 setting the current limit a ratio of isns is also compared to the current established when a 0.9 v internal reference drives the ilim pin. the threshold is determined at the point when the . since therefore , since the tolerance on the current limit is largely dependent on the ratio of the external resistors it is fairly accurate if the v oltage drop on the switching node side of r sense is an accurate representation of the load current. when using the mosfet as the sensing element, the variation of r ds(on) causes proportional variation in the isns. this value not only varies from device to device, but also has a typical junction temperature coef?ient of about 0.4%/? (consult the mosfet datasheet for actual values), so the actual current limit set point will decrease proportional to increas- ing mosfet die temperature. a factor of 1.6 in the current limit setpoint should compensate for all mosfet r ds(on) v ariations, assuming the mosfets heat sinking will keep its operating die temperature below 125?. figure 11. improving current sensing accuracy more accurate sensing can be achieved by using a resistor (r1) instead of the r ds(on) of the fet as shown in figure 11. this approach causes higher losses, but yields greater accuracy in both v droop and i limit . r1 is a low value (e.g. 10m ? ) resistor. current limit (i limit ) should be set suf?iently high as to allow inductor current to rise in response to an output load transient. typically, a factor of 1.3 is suf?ient. in addition, since i limit is a peak current cut-off value, we will need to multiply i load(max) by the inductor ripple current (we'll use 25%). for example, in figure 5 the target for i limit w ould be: i limit > 1.2 1.25 1.6 6a 14a (4) gate driver section the adaptive gate control logic translates the internal pwm control signal into the mosfet gate drive signals providing necessary ampli?ation, level shifting and shoot-through protection. also, it has functions that help optimize the ic performance over a wide range of operating conditions. since mosfet switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to- source voltages of both upper and lower mosfets. the lower mosfet drive is not turned on until the gate-to- source voltage of the upper mosfet has decreased to less than approximately 1 volt. similarly, the upper mosfet is not turned on until the gate-to-source voltage of the lower mosfet has decreased to less than approximately 1 volt. this allows a wide variety of upper and lower mosfets to be used without a concern for simultaneous conduction, or shoot-through. there must be a low-resistance, low-inductance path between the driver pin and the mosfet gate for the adap- tive dead-time circuit to work properly. any delay along that path will subtract from the delay generated by the adaptive dead-time circuit and shoot-through may occur. frequency loop compensation due to the implemented current mode control, the modulator has a single pole response with -1 slope at frequency deter- mined by load where r o is load resistance, c o is load capacitance. for this type of modulator, type 2 compensation circuit is usually suf?ient. to reduce the number of external components and simplify the design task, the pwm controller has an inter- nally compensated error ampli?r. figure 12 shows a type 2 ampli?r and its response along with the responses of a current mode modulator and of the converter. the type 2 ampli?r, in addition to the pole at the origin, has a zero-pole pair that causes a ?t gain region at frequencies between the zero and the pole. this region is also associated with phase ?ump or reduced phase shift. the amount of phase shift reduction depends the width of the region of ?t gain and has a maximum value of 90 degrees. to further simplify the converter compensation, the modulator gain is kept independent of the input voltage v ariation by providing feed-forward of vin to the oscillator ramp. isns 9 ------------- - ilim 4 3 ---------------------- - > isns i load r ds on () 100 r + sense ------------------------------------------- - = i limit 0.9v r ilim -------------- - 4 3 -- - 9 100 r sense + () r ds on () ------------------------------------------------- = (3a) or r ilim 11.2 i limit ---------------- 100 r sense + () r ds on () --------------------------------------- - = (3b) ldrv pgnd isns r sens e r1 q2 f po 1 2 r o c o ---------------------- = (5) f z 1 2 r 2 c 1 -- -- - --- -- -- --- -- -- - 6khz == (6a) f p 1 2 r 2 c 2 - --- -- -- --- -- -- -- -- - 60 0khz == (6b)
product specification FAN5026 12 rev. 1.0.2b 9/2/03 figure 12. compensation the zero frequency, the ampli?r high frequency gain and the modulator gain are chosen to satisfy most typical appli- cations. the crossover frequency will appear at the point where the modulator attenuation equals the ampli?r high frequency gain. the only task that the system designer has to complete is to specify the output ?ter capacitors to position the load main pole somewhere within one decade lower than the ampli?r zero frequency. with this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase ?oost? conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output ?ter capacitance. in this case, the esr zero placed within the 10khz...50khz range gives some additional phase ?oost? fortunately, there is an oppo- site trend in mobile applications to keep the output capacitor as small as possible. if a larger inductor value or low esr values are called for by the application, additional phase margin can be achieved by putting a zero at the lc crossover frequency. this can be achieved with a capacitor across the feedback resistor (e.g. r5 from figure 5) as shown below. figure 13. improving phase margin the optimal value of c(z) is: protection the converter output is monitored and protected against e xtreme overload, short circuit, over-voltage and under- v oltage conditions. a sustained overload on an output sets the pgx pin low and latches-off the whole chip. operation can be restored by c ycling the vcc voltage or by toggling the en pin. if vout drops below the under-voltage threshold, the chip shuts down immediately. over-current sensing if the circuits current limit signal (?lim det?as shown in figure 10) is high at the beginning of a clock cycle, a pulse- skipping circuit is activated and hdrv is inhibited. the cir- cuit continues to pulse skip in this manner for the next 8 clock cycles. if at any time from the 9 th to the 16 th clock c ycle, the ?lim det?is again reached, the over-current pro- tection latch is set, disabling the chip. if ?lim det?does not occur between cycle 9 and 16, normal operation is restored and the over-current circuit resets itself. figure 14. over-current protection waveforms over-voltage / under-voltage protection should the vsns voltage exceed 120% of vref (0.9v) due to an upper mosfet failure, or for other reasons, the over- v oltage protection comparator will force ldrv high. this action actively pulls down the output voltage and, in the ev ent of the upper mosfet failure, will eventually blow the battery fuse. as soon as the output voltage drops below the threshold, the ovp comparator is disengaged. this ovp scheme provides a ?oft crowbar function which helps to tackle severe load transients and does not invert the output voltage when activated ?a common problem for latched ovp schemes. similarly, if an output short-circuit or severe load transient causes the output to droop to less than 75% of its regulation set point. should this condition occur, the regulator will shut down. r1 r2 ea out c1 c2 re f v in c o nv e r t er 0 14 18 modulator f p0 f z f p e rr o r a m p c(out) vout c(z) r5 vsen l(out) r6 cz () l out () c out () r5 ------------------------------------------------------ = (7) 1 2 3 ch1 5.0v ch3 2.0a ? ch2 100mv m 10.0 s il shutdown pgood 8 clk vout
FAN5026 product specification rev. 1.0.2b 9/2/03 13 over-temperature protection the chip incorporates an over temperature protection circuit that shuts the chip down when a die temperature of about 150? is reached. normal operation is restored at die temperature below 125? with internal power on reset asserted, resulting in a full soft-start cycle. design and component selection guidelines as an initial step, de?e operating input voltage range, output voltage, minimum and maximum load currents for the controller. setting the output voltage the internal reference is 0.9v. the output is divided down by a voltage divider to the vsen pin (for example, r5 and r6 in figure 4). the output voltage therefore is: to minimize noise pickup on this node, keep the resistor to gnd (r6) below 2k. we selected r6 at 1.82k. then choose r5: f or ddr applications converting from 3.3v to 2.5v, or other applications requiring high duty cycles, the duty cycle clamp must be disabled by tying the converters fpwm to gnd. when converters fpwm is gnd, the converter's maximum duty cycle will be greater than 90%. when using as a ddr converter with 3.3v input, set up the converter for in-phase synchronization by tying the vin pin to +5v. output inductor selection the minimum practical output inductor value is the one that k eeps inductor current just on the boundary of continuous conduction at some minimum load. the industry standard practice is to choose the minimum current somewhere from 15% to 35% of the nominal current. at light load, the controller can automatically switch to hysteretic mode of operation to sustain high ef?iency. the following equations help to choose the proper value of the output ?ter inductor. where ? i is the inductor ripple current and ? v out is the maximum ripple allowed. for this example well use: v in = 12v, v out = 2.5v ? i = 25% 6a = 1.5a f sw = 300khz. therefore l 4.4 h output capacitor selection the output capacitor serves two major functions in a switching power supply. along with the inductor it ?ters the sequence of pulses produced by the switcher, and it supplies the load transient currents. the output capacitor require- ments are usually dictated by esr, inductor ripple current ( ? i) and the allowable ripple voltage ( ? v). in addition, the capacitors esr must be low enough to allow the converter to stay in regulation during a load step. the ripple voltage due to esr for the converter in figure 5 is 120mv p-p. some additional ripple will appear due to the capacitance value itself: which is only about 1.5mv for the converter in figure 5 and can be ignored. the capacitor must also be rated to withstand the rms current which is approximately 0.3 x ( ? i), or about 400ma for the converter in figure 5. high frequency decoupling capacitors should be placed as close to the loads as physically possible. input capacitor selection the input capacitor should be selected by its ripple current rating. tw o-stage converter case in ddr mode (figure 4), the vtt power input is powered by the vddq output, therefore all of the input capacitor ripple current is produced by the vddq converter. a conser- v ative estimate of the output current required for the 2.5v regulator is: as an example, if average i vddq is 3a, and average i vtt is 1a, i vddq current will be about 3.5a. if average input v oltage is 12v, rms input ripple current will be: 0.9v r6 ----------- - v out 0.9v r5 -------------------------------- - = (8a) r5 1.82k () v out 0.9 () 0.9 -- -- - --- -- -- --- -- -- -- --- -- -- --- -- -- --- -- -- -- --- -- -- --- -- -- - 3.24k == (8b) ? i2i min ? v out esr ------------------ == (9) l v in v out f sw ? i ------------------------------ v out v in -------------- = (10) esr ? v ? i ------- - < (11) ? v ? i c out 8 f sw ---------------------------------------- - = (12) i reg1 i vddq i vtt 2 ----------- - + = i rms i out max () dd 2 = (13)
product specification FAN5026 14 rev. 1.0.2b 9/2/03 where d is the duty cycle of the pwm1 converter: therefore: dual converter 180?phased in dual mode (figure 5), both converters contribute to the capacitor input ripple current. with each converter operating 180?out of phase, the rms currents add in the following f ashion: which for the dual 3a converters of figure 5, calculates to: po wer mosfet selection losses in a mosfet are the sum of its switching (p sw ) and conduction (p cond ) losses. in typical applications, the FAN5026 converters output v oltage is low with respect to its input voltage, therefore the lower mosfet (q2) is conducting the full load current for most of the cycle. q2 should therefore be selected to mini- mize conduction losses, thereby selecting a mosfet with low r ds(on) . in contrast, the high-side mosfet (q1) has a much shorter duty cycle, and it's conduction loss will therefore have less of an impact. q1, however, sees most of the switching losses, so q1s primary selection criteria should be gate charge. high-side losses figure 15 shows a mosfets switching interval, with the upper graph being the voltage and current on the drain to source and the lower graph detailing v gs vs. time with a constant current charging the gate. the x-axis therefore is also representative of gate charge (q g ). c iss = c gd + c gs , and it controls t1, t2, and t4 timing. c gd receives the current from the gate driver during t3 (as v ds is falling). the gate charge (q g ) parameters on the lower graph are either speci- ?d or can be derived from mosfet datasheets. assuming switching losses are about the same for both the rising edge and falling edge, q1s switching losses, occur during the shaded time when the mosfet has voltage across it and current through it. these losses are given by: p upper = p sw + p cond where: p upper is the upper mosfets total losses, and p sw and p cond are the switching and conduction losses for a given mosfet. r ds(on) is at the maximum junction temperature (t j ). t s is the switching period (rise or fall time) and is t2+t3 figure 15. the drivers impedance and c iss determine t2 while t3s period is controlled by the driver's impedance and q gd . since most of t s occurs when v gs = v sp we can use a constant current assumption for the driver to simplify the calculation of t s : figure 15. switching losses and q g figure 16. drive equivalent circuit d v out v in -------------- < 2.5 12 ------- = (14) i rms 3.5 2.5 12 ------- 2.5 12 ------- ?? ?? 2 1.42a == (15) i rms i rms 1 () 2 i rms 2 () 2 + or = (16a) i rms i 1 () 2 d 1 d 1 2 () i 2 () 2 d 2 d 2 2 () + = (16b) i rms 1.51a = p sw v ds i l 2 --------------------- - 2 t s ?? ?? f sw = (17a) p cond v out v in -------------- ?? ?? i out 2 r ds on () = (17b) v sp t1 t2 t3 4.5v t4 t5 q g (sw) v ds i d q gs q gd v th v gs c iss c gd c is s c gd r d r gate c gs hd rv 5v sw vi n g t s q gsw () i driver -------------------- - q gsw () vcc v sp r driver r gate + ----------------------------------------------- ?? ?? ---------------------------------------------------- - = (18)
FAN5026 product specification rev. 1.0.2b 9/2/03 15 most mosfet vendors specify q gd and q gs . q g(sw) can be determined as: q g(sw) = q gd + q gs ?q th where q th is the gate charge required to get the mosfet to its threshold (v th ). for the high-side mosfet, v ds = vin, which can be as high as 20v in a typical portable application. care should also be taken to include the delivery of the mos- fets gate power (p gate ) in calculating the power dissipa- tion required for the FAN5026: p gate = q g vcc f sw (19) where q g is the total gate charge to reach vcc. low-side losses q2, however, switches on or off with its parallel shottky diode conducting, therefore v ds 0.5v. since p sw is proportional to v ds , q2s switching losses are negligible and we can select q2 based on r ds(on) only. conduction losses for q2 are given by: where r ds(on) is the r ds(on) of the mosfet at the highest operating junction temperature and is the minimum duty cycle for the converter. since d min < 20% for portable computers, (1?) 1 produces a conservative result, further simplifying the calculation. the maximum power dissipation (p d(max) ) is a function of the maximum allowable die temperature of the low-side mosfet, the j-a , and the maximum allowable ambient temperature rise: j-a , depends primarily on the amount of pcb area that can be devoted to heat sinking (see fsc app note an-1029 for so-8 mosfet thermal information). layout considerations switching converters, even during normal operation, produce short pulses of current which could cause substan- tial ringing and be a source of emi if layout constrains are not observed. there are two sets of critical components in a dc-dc converter. the switching power components process large amounts of energy at high rate and are noise generators. the low power components responsible for bias and feed- back functions are sensitive to noise. a multi-layer printed circuit board is recommended. dedicate one solid layer for a ground plane. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. notice all the nodes that are subjected to high dv/dt voltage swing such as sw, hdrv and ldrv, for example. all surrounding circuitry will tend to couple the signals from these nodes through stray capacitance. do not oversize copper traces connected to these nodes. do not place traces connected to the feedback components adjacent to these traces. it is not recommended to use high density intercon- nect systems, or micro-vias on these signals. the use of blind or buried vias should be limited to the low current signals only. the use of normal thermal vias is left to the discretion of the designer. k eep the wiring traces from the ic to the mosfet gate and source as short as possible and capable of handling peak currents of 2a. minimize the area within the gate-source path to reduce stray inductance and eliminate parasitic ringing at the gate. locate small critical components like the soft-start capacitor and current sense resistors as close as possible to the respec- tive pins of the ic. the FAN5026 utilizes advanced packaging technologies with lead pitches of 0.6mm. high performance analog semiconductors utilizing narrow lead spacing may require special considerations in pwb design and manufacturing. it is critical to maintain proper cleanliness of the area surrounding these devices. it is not recommended to use any type of rosin or acid core solder, or the use of ?x in either the manufacturing or touch up process as these may contrib- ute to corrosion or enable electromigration and/or eddy currents near the sensitive low current signals. when chemicals such as these are used on or near the pwb, it is suggested that the entire pwb be cleaned and dried completely before applying power. p cond 1d () i out 2 r ds on () = (20) d v out v in -------------- = p dmax () t jmax () t a max () ja ------------------------------------------------- - = (21)
product specification FAN5026 16 rev. 1.0.2b 9/2/03 mechanical dimensions 28-pin tssop 9.7 0.1 15 ?b 0.1 c pin # 1 ident 14 all lead tips 0.2 land pattern recommendation 0.65 0.42 ba ?a 4.4 0.1 1.78 4.16 7.72 0.51 typ 28 3.2 6.4 1.2 max all lead tips 0.65 0.19?.30 0.13 0.90 see detail a 0.09?.20 0.10 0.05 0 ? r0.31 r0.16 .025 gage plane seating plane detail a 0.61 0.1 dimensions are in millimeters notes: a. conforms to jedec registration mo-153, variation ab, ref. note 6, dated 7/93. b. dimensions are in millimeters. c. dimensions are exclusive of burrs, mold flash, and tie bar extensions. d dimensions and tolerances per ansi y14.5m, 1982 1.00 12.00 t op & botom +0.15 ?.10 bc a ?c
product specification FAN5026 life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 9/2/03 0.0m 004 stock#ds30005026 ? 2003 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. ordering information pa rt number temperature range package packing f an5026mtc -40? to 85? tssop-28 rails f an5026mtcx -40? to 85? tssop-28 tape and reel

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